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1. Several specifications can only be measured when the MC88915TFN55, 70 and 100 are in phaselocked operation. It is not possible to have the part in phaselock on ATE (automated test equipment). Statistical characterization techniques were used to guarantee those specifications which cannot be measured on the ATE. MC88915TFN55, 70 and 100 units were fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix. IC performance was characterized over a range of transistor properties (represented by the 14 cells) in excess of the expected process variation of the wafer fabrication area, to set performance limits of ATE testable specifications within those which are to be guaranteed by statistical characterization. In this way all units passing the ATE test will meet or exceed the nontested specifications limits.2. These two specs (tRlSE/FALL and tPULSE Width 2X_Q output) guarantee that the MC88915T meets the 40MHzand 33MHz MC68040 PClock input specification (at 80MHz and 66MHz, respectively). For these two specs tobe guaranteed by Motorola, the termination scheme shown below in Figure 1 must be used.3. The wiring Diagrams and explanations in Figure 5 demonstrate the input and output frequency relationshipsfor three possible feedback configurations. The allowable SYNC input range for each case is also indicated. Thereare two allowable SYNC frequency ranges, depending whether FREQ_SEL is high or low. Although not shown, itis possible to feed back the Q5 output, thus creating a 180° phase shift between the SYNC input and the "Q"outputs. Table 1 below summarizes the allowable SYNC frequency range for each possible configuration.
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• Five Outputs (Q0Q4) with OutputOutput Skew < 500 ps each being phase and frequency locked to the SYNC input• The phase variation from parttopart between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which defines the parttopart skew)• Input/Output phaselocked frequency ratios of 1:2, 1:1, and 2:1 are available• Input frequency range from 5MHz 2X_Q FMAX spec. (10MHz 2X_Q FMAX for the TFN133 version)• Additional outputs available at 2X and +2 the system "Q" frequency. Also a Q(180° phase shift) output available• All outputs have ±36 mA drive (equal high and low) at CMOS levels, and can drive either CMOS or TTL inputs. All inputs are TTLlevel compatible. ±88mA IOL/IOH specifications guarantee 50 transmission line switching on the incident edge• Test Mode pin (PLL_EN) provided for low frequency testing. Two selectable CLOCK inputs for test or redundancy purposes. All outputs can go into high impedance (3state) for board test purposes• Lock Indicator (LOCK) accuracy indicates a phaselocked state
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Required Field 
